1. Field of the Invention
The present invention relates to a frequency synthesizer, and in particular to an improved coherent frequency synthesizer which can be implemented using a 0.8 .mu.m CMOS integration technique, and which is adaptable to a mobile communication transceiver.
2. Description of the Conventional Art
Recently, wire less communication becomes more important in the information communication field. The number of subscribers to mobile communication systems adapting an analog technique has sharply increased due to its convenience; however, due to the limited capacity of the systems adapting the analog technique with a heavy communications load and the sharply increasing number of the subscribers, mobile communication systems adapting a digital technique were developed in an attempt to overcome the above-described limitation.
In a digital cellular communication system, many people can concurrently use the system within a limited frequency spectrum, and various kinds of digital information can be made available for subscribers, and it is possible to effectively achieve a desired security of the communication.
This type of mobile communication system includes a frequency synthesizer for generating a new frequency based on a reference frequency, with the reference frequency being stable accurate and having a pure spectrum.
The frequency synthesizer is generally implemented as a phase locked loop (PLL) since the cost of implementing the phase locked loop as a circuit for generating frequencies is low, and the spectrum purity is high.
The frequency synthesizer exhibits jitter noise which is classified into input jitter and output jitter and which has a close relationship to the loop bandwidth of the phase locked loop (PLL).
Namely, when the loop bandwidth is narrow, it is easy to remove the input jitter, however the jitter is increased due to the voltage controlled oscillator VCO since the tracking is lower. On the contrary, when the loop bandwidth is wide, the jitter is decreased due to the VCO, and it is difficult to remove the input jitter.
Therefore, in order to implement a frequency synthesizer having low jitter, the loop bandwidth of the phase locked loop (PLL) should be optimized.
In addition, in the output phase noise, at a lower frequency, the jitter noise is dependent upon a crystal oscillator, and at a higher frequency, the jitter noise is dependent upon the voltage controlled oscillator (VCO).
Here, since the jitter noise due to the crystal oscillator is smaller than the jitter noise due to the voltage controlled oscillator, the jitter noise characteristic of the frequency synthesizer is determined entirely by the jitter noise characteristic due to the voltage controlled oscillator (VCO).
Therefore, designing the voltage controlled oscillator (VCO) to have a low jitter noise is very important.
Namely, when implementing the phase locked loop (PLL), the design conditions of the voltage controlled oscillator and frequency divider are important factors in determining its speed and power consumption.
So far, the voltage controlled oscillator and the frequency divider having a higher frequency bandwidth have been implemented using a high speed chip integration technique such as ECL or GaAs. However, as the techniques related thereto have advanced, CMOS devices have been made compact-sized, and CMOS circuits having high speed characteristics are being made.
Namely, when using the oscillator in order to match a transmitter and a receiver of the frequency synthesizer, so far, an LC tank oscillator using a varactor has been used. However, the cost of the LC tank oscillator is high, and a high power consumption is incurred. In addition, the bulk and weight of the transceiver are increased. So as to overcome the above-described problems, a CMOS ring oscillator, which is capable of reduced power consumption, circuit integration, and having a high reliability has been introduced.
However, the above-described CMOS ring oscillator may degrade the performance of the frequency synthesizer since its is susceptible to power supply noise.
In addition, a CMOS voltage controlled oscillator (VCO), which is resistant to power supply noise and is directed to enhancing the temperature characteristic and is similar to an ECL type has been introduced. However, this CMOS voltage controlled oscillator (VCO) is not adaptable to mobile communications since he operating frequency is low.
In addition, a method of adapting a CMOS prescaler to the frequency divider has been introduced. However, this method is only directed to reducing the size of the device. In addition, a prescaler method using a dynamic circuit technique has been introduced. This method operates well at a high frequency; however, it is susceptible to the noise of the dynamic circuit.